Often, a computer system includes a controller, such as a micro-processor, and one or more memory chips, such as dynamic random access memory (DRAM) chips. The DRAM chips can be any suitable type of DRAM, such as double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), low power DDR-SDRAM (LPDDR-SDRAM), reduced latency DRAM (RLDRAM), and pseudo-static RAM (PSRAM) that is based on DRAM. The PSRAM provides advantages in density and speed over traditional static RAM (SRAM).
Typically, a DRAM includes one transistor and one capacitor memory cells arranged in one or more arrays of memory cells, which are arranged in memory banks. Conductive word lines, referred to as row select lines, extend in one direction across an array of memory cells and conductive bit lines, referred to as digit select lines, extend in another direction across the array of memory cells. Memory cells are located at the cross points of word lines and bit lines.
A DRAM includes one or more row decoders, one or more column decoders, and sense amplifiers. To read or write memory cells, the DRAM receives a row address, a column address, and control signals, such as row address select (RAS) and column address select (CAS) signals. A row decoder receives the row address to select a word line or row of memory cells and the row address is latched into the row decoder via the RAS signal. A column decoder receives the column address to select one or more bit lines or columns of memory cells and the column address is latched into the column decoder via the CAS signal. Memory cells at the intersection of the selected row and the selected columns provide data bit values.
The sense amplifiers can be differential sense amplifiers, wherein each sense amplifier receives complementary bit lines at differential inputs. Typically, the complementary bit lines and the sense amplifier are equalized to each other and to an equalization voltage, VBLEQ, during an idle or pre-charge state of the DRAM. The equalization voltage prepares the bit lines and sense amplifier for the next sensing operation. At the sense amplifier, one of the bit lines receives a data bit value from a selected memory cell and the other bit line is used as a reference.
To read the data bit, the sense amplifier amplifies the difference between the data bit value and the reference value and provides a sensed output value to an output driver. The sensed output value is stored back in the selected memory cell at the end of the read operation. To write a data bit into a selected memory cell, input drivers overdrive the sense amplifier. One input driver overdrives a data bit value onto the bit line that is connected to the selected memory cell and another input driver overdrives the inverse of the data bit value onto the reference bit line. Usually, two pairs of bit lines are multiplexed onto the differential inputs of a sense amplifier and an equalization circuit is placed across each pair of complementary bit lines. Often, each of the memory cells is refreshed via a read operation.
Self-refresh mode is an important low power mode in DRAM chips. During an idle state between refresh cycles, both of the equalization circuits are activated and the bit lines on each side of the sense amplifier are connected together and to the sense amplifier to equalize the voltage to VBLEQ. This equalization voltage prepares the bit lines and sense amplifiers for the next refresh. Also, during the idle state the word lines are held at a word line voltage that is usually different than the equalization voltage, VBLEQ.
One of the yield detractors in DRAM production is word line to bit line shorts. The word line to bit line shorts connect the VBLEQ voltage source to the word line voltage source during the idle state, which causes an increase in standby current that may violate current specifications.
For these and other reasons there is a need for the present invention.